* [gentoo-commits] proj/catalyst:2.X commit in: arch/
@ 2015-02-10 11:54 Anthony G. Basile
0 siblings, 0 replies; 2+ messages in thread
From: Anthony G. Basile @ 2015-02-10 11:54 UTC (permalink / raw
To: gentoo-commits
commit: 1082054caa75f3162fdad811d787aaffe3d7d643
Author: Joshua Kinard <kumba <AT> gentoo <DOT> org>
AuthorDate: Tue Feb 10 11:57:18 2015 +0000
Commit: Anthony G. Basile <blueness <AT> gentoo <DOT> org>
CommitDate: Tue Feb 10 11:57:18 2015 +0000
URL: http://sources.gentoo.org/gitweb/?p=proj/catalyst.git;a=commit;h=1082054c
arch/mips.py: update MIPS targets
Signed-off-by: Anthony G. Basile <blueness <AT> gentoo.org>
---
arch/mips.py | 96 +++++++++++++++++++++++++++++++++++++++++++-----------------
1 file changed, 69 insertions(+), 27 deletions(-)
diff --git a/arch/mips.py b/arch/mips.py
index b3730fa..1eb2e5c 100644
--- a/arch/mips.py
+++ b/arch/mips.py
@@ -36,6 +36,12 @@ class arch_mips1(generic_mips):
generic_mips.__init__(self,myspec)
self.settings["CFLAGS"]="-O2 -march=mips1 -mabi=32 -mplt -pipe"
+class arch_mips2(generic_mips):
+ "Builder class for MIPS II [Big-endian]"
+ def __init__(self,myspec):
+ generic_mips.__init__(self,myspec)
+ self.settings["CFLAGS"]="-O2 -march=mips2 -mabi=32 -mplt -pipe"
+
class arch_mips32(generic_mips):
"Builder class for MIPS 32 [Big-endian]"
def __init__(self,myspec):
@@ -134,6 +140,30 @@ class arch_mips4_r10k_multilib(generic_mips64):
generic_mips64.__init__(self,myspec)
self.settings["CFLAGS"]="-O2 -march=r10k -mplt -pipe"
+class arch_mips4_r12k(generic_mips):
+ "Builder class for MIPS IV R12k/R14k/R16k [Big-endian]"
+ def __init__(self,myspec):
+ generic_mips.__init__(self,myspec)
+ self.settings["CFLAGS"]="-O2 -march=r12k -mno-fix-r10000 -mabi=32 -mplt -pipe"
+
+class arch_mips4_r12k_n32(generic_mips64):
+ "Builder class for MIPS IV R12k/R14k/R16k [Big-endian N32]"
+ def __init__(self,myspec):
+ generic_mips64.__init__(self,myspec)
+ self.settings["CFLAGS"]="-O2 -march=r12k -mno-fix-r10000 -mabi=n32 -mplt -pipe"
+
+class arch_mips4_r12k_n64(generic_mips64):
+ "Builder class for MIPS IV R12k/R14k/R16k [Big-endian N64]"
+ def __init__(self,myspec):
+ generic_mips64.__init__(self,myspec)
+ self.settings["CFLAGS"]="-O2 -march=r12k -mno-fix-r10000 -mabi=64 -pipe"
+
+class arch_mips4_r12k_multilib(generic_mips64):
+ "Builder class for MIPS IV R12k/R14k/R16k [Big-endian multilib]"
+ def __init__(self,myspec):
+ generic_mips64.__init__(self,myspec)
+ self.settings["CFLAGS"]="-O2 -march=r12k -mno-fix-r10000 -mplt -pipe"
+
class arch_mips64(generic_mips):
"Builder class for MIPS 64 [Big-endian]"
def __init__(self,myspec):
@@ -188,6 +218,12 @@ class arch_mipsel1(generic_mipsel):
generic_mipsel.__init__(self,myspec)
self.settings["CFLAGS"]="-O2 -march=mips1 -mabi=32 -mplt -pipe"
+class arch_mipsel2(generic_mipsel):
+ "Builder class for MIPS II [Little-endian]"
+ def __init__(self,myspec):
+ generic_mipsel.__init__(self,myspec)
+ self.settings["CFLAGS"]="-O2 -march=mips2 -mabi=32 -mplt -pipe"
+
class arch_mips32el(generic_mipsel):
"Builder class for MIPS 32 [Little-endian]"
def __init__(self,myspec):
@@ -399,66 +435,72 @@ class arch_cobalt_n32(generic_mips64el):
def register():
"Inform main catalyst program of the contents of this plugin."
return ({
- "cobalt" : arch_cobalt,
+ "cobalt" : arch_cobalt,
"cobalt_n32" : arch_cobalt_n32,
- "mips" : arch_mips1,
- "mips1" : arch_mips1,
- "mips32" : arch_mips32,
+ "mips" : arch_mips1,
+ "mips1" : arch_mips1,
+ "mips2" : arch_mips2,
+ "mips32" : arch_mips32,
"mips32_softfloat" : arch_mips32_softfloat,
- "mips32r2" : arch_mips32r2,
- "mips32r2_softfloat" : arch_mips32r2_softfloat,
- "mips3" : arch_mips3,
- "mips3_n32" : arch_mips3_n32,
- "mips3_n64" : arch_mips3_n64,
+ "mips32r2" : arch_mips32r2,
+ "mips32r2_softfloat" : arch_mips32r2_softfloat,
+ "mips3" : arch_mips3,
+ "mips3_n32" : arch_mips3_n32,
+ "mips3_n64" : arch_mips3_n64,
"mips3_multilib" : arch_mips3_multilib,
- "mips4" : arch_mips4,
- "mips4_n32" : arch_mips4_n32,
- "mips4_n64" : arch_mips4_n64,
+ "mips4" : arch_mips4,
+ "mips4_n32" : arch_mips4_n32,
+ "mips4_n64" : arch_mips4_n64,
"mips4_multilib" : arch_mips4_multilib,
"mips4_r10k" : arch_mips4_r10k,
"mips4_r10k_n32" : arch_mips4_r10k_n32,
"mips4_r10k_n64" : arch_mips4_r10k_n64,
- "mips4_r10k_multilib" : arch_mips4_r10k_multilib,
- "mips64" : arch_mips64,
+ "mips4_r10k_multilib" : arch_mips4_r10k_multilib,
+ "mips4_r12k" : arch_mips4_r12k,
+ "mips4_r12k_n32" : arch_mips4_r12k_n32,
+ "mips4_r12k_n64" : arch_mips4_r12k_n64,
+ "mips4_r12k_multilib" : arch_mips4_r12k_multilib,
+ "mips64" : arch_mips64,
"mips64_n32" : arch_mips64_n32,
"mips64_n64" : arch_mips64_n64,
"mips64_multilib" : arch_mips64_multilib,
- "mips64r2" : arch_mips64r2,
+ "mips64r2" : arch_mips64r2,
"mips64r2_n32" : arch_mips64r2_n32,
"mips64r2_n64" : arch_mips64r2_n64,
"mips64r2_multilib" : arch_mips64r2_multilib,
- "mipsel" : arch_mipsel1,
- "mipsel1" : arch_mipsel1,
- "mips32el" : arch_mips32el,
- "mips32el_softfloat" : arch_mips32el_softfloat,
+ "mipsel" : arch_mipsel1,
+ "mipsel1" : arch_mipsel1,
+ "mipsel2" : arch_mipsel2,
+ "mips32el" : arch_mips32el,
+ "mips32el_softfloat" : arch_mips32el_softfloat,
"mips32r2el" : arch_mips32r2el,
- "mips32r2el_softfloat" : arch_mips32r2el_softfloat,
- "mipsel3" : arch_mipsel3,
+ "mips32r2el_softfloat" : arch_mips32r2el_softfloat,
+ "mipsel3" : arch_mipsel3,
"mipsel3_n32" : arch_mipsel3_n32,
"mipsel3_n64" : arch_mipsel3_n64,
"mipsel3_multilib" : arch_mipsel3_multilib,
- "mipsel4" : arch_mipsel4,
+ "mipsel4" : arch_mipsel4,
"mipsel4_n32" : arch_mipsel4_n32,
"mipsel4_n64" : arch_mipsel4_n64,
"mipsel4_multilib" : arch_mipsel4_multilib,
- "mips64el" : arch_mips64el,
+ "mips64el" : arch_mips64el,
"mips64el_n32" : arch_mips64el_n32,
"mips64el_n64" : arch_mips64el_n64,
"mips64el_multilib" : arch_mips64el_multilib,
"mips64r2el" : arch_mips64r2el,
"mips64r2el_n32" : arch_mips64r2el_n32,
"mips64r2el_n64" : arch_mips64r2el_n64,
- "mips64r2el_multilib" : arch_mips64r2el_multilib,
+ "mips64r2el_multilib" : arch_mips64r2el_multilib,
"loongson2e" : arch_loongson2e,
"loongson2e_n32" : arch_loongson2e_n32,
"loongson2e_n64" : arch_loongson2e_n64,
- "loongson2e_multilib" : arch_loongson2e_multilib,
+ "loongson2e_multilib" : arch_loongson2e_multilib,
"loongson2f" : arch_loongson2f,
"loongson2f_n32" : arch_loongson2f_n32,
"loongson2f_n64" : arch_loongson2f_n64,
- "loongson2f_multilib" : arch_loongson2f_multilib,
+ "loongson2f_multilib" : arch_loongson2f_multilib,
"loongson3a" : arch_loongson3a,
"loongson3a_n32" : arch_loongson3a_n32,
"loongson3a_n64" : arch_loongson3a_n64,
- "loongson3a_multilib" : arch_loongson3a_multilib,
+ "loongson3a_multilib" : arch_loongson3a_multilib,
}, ("mips","mips64"))
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [gentoo-commits] proj/catalyst:2.X commit in: arch/
@ 2015-09-22 22:38 Anthony G. Basile
0 siblings, 0 replies; 2+ messages in thread
From: Anthony G. Basile @ 2015-09-22 22:38 UTC (permalink / raw
To: gentoo-commits
commit: d6b7b3148e604a01f2be24324f1d351fd4f72465
Author: Leno Hou <lenohou <AT> gmail <DOT> com>
AuthorDate: Tue Sep 22 22:34:26 2015 +0000
Commit: Anthony G. Basile <blueness <AT> gentoo <DOT> org>
CommitDate: Tue Sep 22 22:41:23 2015 +0000
URL: https://gitweb.gentoo.org/proj/catalyst.git/commit/?id=d6b7b314
Currently catalyst does not support ppc64le arch,
we add subarch power8 to support ppc64le and make stage files.
Signed-off-by: Leno Hou <lenohou <AT> gmail.com>
Signed-off-by: Anthony G. Basile <blueness <AT> gentoo.org>
arch/powerpc.py | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc.py b/arch/powerpc.py
index e9f611b..7cdbe55 100644
--- a/arch/powerpc.py
+++ b/arch/powerpc.py
@@ -105,6 +105,14 @@ class arch_power6(arch_ppc64):
self.settings["CFLAGS"]="-O2 -pipe -mcpu=power6 -mtune=power6"
self.settings["HOSTUSE"]=["altivec","ibm"]
+class arch_power8(arch_ppc64):
+ "builder class for power8 under ppc64le"
+ def __init__(self,myspec):
+ arch_ppc64.__init__(self,myspec)
+ self.settings["CFLAGS"]="-O2 -pipe -mcpu=power8 -mtune=power8 -mabi=elfv2"
+ self.settings["CHOST"]="powerpc64le-unknown-linux-gnu"
+ self.settings["HOSTUSE"]=["altivec","ibm"]
+
def register():
"Inform main catalyst program of the contents of this plugin."
return ({
@@ -119,6 +127,7 @@ def register():
"power4" : arch_power4,
"power5" : arch_power5,
"power6" : arch_power6,
+ "power8" : arch_power8,
"ppc" : arch_ppc,
"ppc64" : arch_ppc64
- }, ("ppc","ppc64","powerpc","powerpc64"))
+ }, ("ppc","ppc64","ppc64le","powerpc","powerpc64","powerpc64le"))
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